This invention relates to both CMOS and bipolar devices and fabrication processes therefor and, in particular, to a process for forming high performance bipolar junction transistors in CMOS integrated circuits.
The original development of monolithic integrated circuits was based upon bipolar junction transistors ("BJT") which were built as vertical NPN devices. With further development of the technology to very large scale integrated (VLSI) circuits, the newer metal-oxide-silicon field effect transistor (MOSFET) device has become predominant due to its inherently lower power dissipation and smaller size. In a continuing effort to improve VLSI circuit performance at lower power and lower cost, the industry has evolved from p-channel MOSFETs (PMOS) to n-channel MOSFETs (NMOS) and now to complementary MOS (CMOS=NMOS+PMOS) circuits and process technologies.
During this evolution of VLSI, the bipolar technologies have dominated most applications that require linear amplification of analog signals. In addition, the bipolar technologies have maintained dominance in those applications that require the utmost in high frequency performance, even at the expense of power dissipation and cost. This dominance is due to the ability of BJTs to rapidly switch relatively large currents with high current gain.
State-of-the-art high performance bipolar junction transistors are described by Graul et al., "High-Performance Transistors with Arsenic-Implanted Polysil Emitters", IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 4, August 1976, pp. 491-495 ("Graul et al"). A primary feature of the fabrication process described by Graul et al. is the formation of the base by a single implantation with boron ions, followed by opening contact windows through a deposited oxide, depositing undoped polycrystalline silicon (hereafter, also "polysilicon") on the water, arsenic implanting the polysilicon, then diffusing the arsenic into the base region to form a shallow emitter and a narrow base width. The advantages of the process, vis a vis conventional double-implanted transistors, include higher current gain, lower base resistance, higher current carrying ability and improved emitter-base breakdown. Since the emitter is formed predominantly in the polysilicon, and since the emitter annealing/diffusion cycle is very brief, the probability of forming emitter-collector shorts due to "diffusion pipes" is minimized and the yield of the process is high.
The excellent current gain of bipolar transistors having shallow emitters was also observed by Ning et al., "Effect of Emitter Contact on Current Gain of Silicon Bipolar Devices", IEEE Transactions on Electron Devices, Vol. ED-27, No. 11, November 1980, pp. 2051-2055 ("Ning et al."). Ning et al. concluded that contact by a thin layer of polycrystalline silicon was a primary factor in the enhanced current gain.
As will be appreciated, certain integrated circuit functions would best be served by combining CMOS and BJT devices in the same monolithic structure. Examples include memory and logic functions, where the CMOS IC is used for all internal circuitry to minimize area and power and the BJTs are used for output buffers to provide high current output from the circuit. Another example is linear circuits, where the CMOS circuits are used for large scale integration, low power, and high input impedance; the BJTs are used in those portions of the circuit requiring matched transistors which precisely track with temperature and have low differential offset voltages. Still other examples are field programmable logic arrays (FPLA) and programmable read only memories (PROM). The CMOS circuits are used for low power peripheral logic and the high current gain BJTs are used to provide sufficient current to blow the programmable fuse links.
Not unexpectedly then, integrated circuit fabrication processes have been developed which allow the fabrication of both CMOS and bipolar devices on the same chip. However, the potential usefulness of the combined integrated circuits due to the unique characteristics of CMOS and bipolar devices is typically achieved at the expense of process complexity and device density. This is believed particularly true where the combined process is derived from bipolar processes. In addition, the combination of the MOS and BJT processes frequently results in sacrifice or compromise in the performance of either or both types of devices.
Perhaps one of the better processes achieved to data is described in Zimmer et al. "A Fully Implanted NMOS, CMOS, Bipolar Technology For VLSI of Analog-Digital Systems," IEEE Journal of Solid-State Circuits, SC-14, No. 2, pp. 312-318 (April, 1979). The Zimmer et al. process is an extension of NMOS technology which involves forming the PMOS transistors and npn bipolar transistors in separate n-wells. This process has the advantage of providing isolated npn transistors, and of being relatively simple. The process is metal gate, however, which compromises performance, and uses a deposited field oxide, which requires relatively large device spacing.